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1. general description the lpc11e3x are an arm cort ex-m0 based, low-cost 32-bit mcu, designed for 8/16-bit microcontroller applications, offering performan ce, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. the lpc11e3x operate at cpu frequencies of up to 50 mhz. the peripheral complement of the lpc11e3x in cludes up to 128 kb of flash memory, up to 12 kb of sram data memory and 4 kb eeprom, one fast-mode plus i 2 c-bus interface, one rs-485/eia-485 usart with support for synchronous mode and smart card interface, two ssp interfaces, four general purpose counter/timers, a 10-bit adc, and up to 54 general purpose i/o pins. the i/o handler is a software library-supported hardware engine that can be used to add performance, connectivity an d flexibility to system designs. it is available on the lpc11e37hfbd64/401. the i/o handler can emulate serial interfaces such as uart, i 2 c, and i 2 s with no or very low additional cpu load and can off-load the cpu by performing processing-intensive functions like dma transfers in hardware. software libraries for multiple i/o handle r applications are available on http://www.lpcware.com . 2. features and benefits ? system: ? arm cortex-m0 processor, running at frequencies of up to 50 mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? non maskable interrupt (nmi) input se lectable from seve ral input sources. ? system tick timer. ? memory: ? up to 128 kb on-chip flash program memo ry with sector (4 kb) and page erase (256 byte) access. ? 4 kb on-chip eeprom data memory; byte erasable and byte programmable; on-chip api support. ? 12 kb sram data memory. ? 16 kb boot rom. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? rom-based 32-bit integer division routines. lpc11e3x 32-bit arm cortex-m0 microcontroller; up to 128 kb flash; up to 12 kb sram and 4 kb eeprom; usart rev. 2.2 ? 14 january 2014 product data sheet
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 2 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller ? debug options: ? standard jtag (joint test action group ) test interface for bsdl (boundary scan description language). ? serial wire debug. ? digital peripherals: ? up to 54 general purpose i/o (gpio) pi ns with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode. ? up to 8 gpio pins can be selected as edge and level sensitive interrupt sources. ? two gpio grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of gpio pins. ? high-current source output driver (20 ma) on one pin. ? high-current sink driver (20 ma) on true open-drain pins. ? four general purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs. ? programmable windowed watchdog timer (wwdt) with a dedicated, internal low-power watchdog oscillator (wdo). ? analog peripherals: ? 10-bit adc with input multip lexing among eight pins. ? serial interfaces: ? usart with fractional baud rate generati on, internal fifo, a full modem control handshake interface, and support for rs-485/9-bit mode and synchronous mode. usart supports an asynchronous smart card interface (iso 7816-3). ? two ssp controllers with fifo an d multi-protocol capabilities. ? i 2 c-bus interface supporting the full i 2 c-bus specification and fast-mode plus with a data rate of up to 1 mb it/s with multiple address recognition and monitor mode. ? i/o handler for hardware emulation of serial interfaces and dma; supported through software libraries.(lpc11e37hfbd64/401 only.) ? clock generation: ? crystal oscillator with an op erating range of 1 mhz to 25 mhz (system oscillator). ? 12 mhz high-frequency internal rc oscilla tor (irc) that can optionally be used as a system clock. ? internal low-power, low-frequency watchdog oscillator (wdo) with programmable frequency output. ? pll allows cpu operation up to the maxi mum cpu rate with the system oscillator or the irc as clock sources. ? clock output function with divi der that can reflec t the crystal oscillator, the main clock, the irc, or the watchdog oscillator. ? power control: ? integrated pmu (power management unit) to minimize power consumption during sleep, deep-sleep, power-down, and deep power-down modes. ? power profiles residing in boot rom prov ide optimized performance and minimized power consumption for any given application through one simple function call. ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down. ? processor wake-up from deep-sleep and power-down modes via reset, selectable gpio pins, or the watchdog interrupt. ? processor wake-up from deep power-down mode using one special function pin.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 3 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller ? power-on reset (por). ? brownout detect with four separate thre sholds for interrup t and forced reset. ? unique device serial number for identification. ? single 3.3 v power supply (1.8 v to 3.6 v). ? temperature range ? 40 ? c to +85 ? c. ? available as lqfp64, lqfp 48, and hvqfn33 packages. 3. applications 4. ordering information ? consumer peripherals ? handheld scanners ? medical ? industrial control table 1. ordering information type number package name description version LPC11E36FBD64/501 lqfp64 plastic low profil e quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc11e36fhn33/501 hvqfn33 plastic thermal enhanc ed very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc11e37fbd48/501 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc11e37fbd64/501 lqfp64 plastic low profil e quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc11e37hfbd64/401 lqfp64 plastic low profil e quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 4 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 4.1 ordering options [1] for general-purpose use. [2] for i/o handler use only. table 2. ordering options type number flash in kb eeprom in kb sram0 in kb sram2 in kb sram1 in kb total sram in kb [1] i/o handler usart i 2 c-bus fm+ ssp adc channels gpio pins LPC11E36FBD64/501 96 4 8 2 2 [1] 12 no 1 1 2 8 54 lpc11e36fhn33/501 96 4 8 2 2 [1] 12 no 1 1 2 8 28 lpc11e37fbd48/501 128 4 8 2 2 [1] 12 no 1 1 2 8 40 lpc11e37fbd64/501 128 4 8 2 2 [1] 12 no 1 1 2 8 54 lpc11e37hfbd64/401 128 4 8 2 2 [2] 10 yes 1 1 2 8 54
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 5 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 5. block diagram (1) not available on hvqfn33 packages. (2) ct16b0_cap1, ct16b1_cap1 available on lqfp64 packag es only; ct32b0_cap1 av ailable lqfp48, and lqfp64 packages only; ct32b1_cap1 avai lable in lqfp64 packages only. (3) lpc11e37hfbd64/401 only. fig 1. block diagram sram 10/12 kb arm cortex-m0 test/debug interface flash 96/128 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions reset swd, jtag lpc11e3x slave slave slave slave rom 16 kb slave ahb-lite bus gpio ports 0/1 clkout irc, wdo system oscillator por pll0 bod 10-bit adc usart/ smartcard interface ad[7:0] rxd txd cts, rts, dtr sclk gpio interrupts 32-bit counter/timer 0 ct32b0_mat[3:0] ct32b0_cap[1:0] (2) 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap[1:0] (2) dcd, dsr (1) , ri (1) 16-bit counter/timer 1 windowed watchdog timer gpio group0 interrupts ct16b1_mat[1:0] 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap[1:0] (2) ct16b1_cap[1:0] (2) gpio pins gpio pins gpio group1 interrupts gpio pins system bus ssp0 sck0, ssel0, miso0, mosi0 ssp1 sck1, ssel1, miso1, mosi1 i 2 c-bus iocon system control pmu scl, sda xtalin xtalout 002aah401 eeprom 4 kb master i/o handler (3) ioh_[20:0]
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 6 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 pinning for parts lpc11e36fhn33/501 fig 2. pin configuration (hvqfn33) 002aah404 transparent top view pio0_8/miso0/ct16b0_mat0 pio0_20/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio0_22/ad6/ct16b1_mat1/miso1 xtalin tdi/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 tms/pio0_12/ad1/ct32b1_cap0 reset/pio0_0 tdo/pio0_13/ad2/ct32b1_mat0 pio1_19/dtr/ssel1 trst/pio0_14/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio0_21/ct16b1_mat0/mosi1 pio1_23/ct16b1_mat1/ssel1 pio1_24/ct32b0_mat0 pio0_6/sck0 pio0_7/cts pio0_19/txd/ct32b0_mat1 pio0_18/rxd/ct32b0_mat0 pio0_17/rts/ct32b0_cap0/sclk v dd pio1_15/dcd/ct16b0_mat2/sck1 pio0_23/ad7 pio0_16/ad5/ct32b1_mat3/wakeup swdio/pio0_15/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 7 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller fig 3. pin configuration (lqfp48) lpc11e37fbd48/501 pio1_25/ct32b0_mat1 pio1_13/dtr/ct16b0_mat0/txd pio1_19/dtr/ssel1 trst/pio0_14/ad3/ct32b1_mat1 reset/pio0_0 tdo/pio0_13/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 tms/pio0_12/ad1/ct32b1_cap0 v ss tdi/pio0_11/ad0/ct32b0_mat3 xtalin pio1_29/sck0/ct32b0_cap1 xtalout pio0_22/ad6/ct16b1_mat1/miso1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio0_20/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio1_26/ct32b0_mat2/rxd pio1_21/dcd/miso1 pio1_27/ct32b0_mat3/txd pio1_31 pio1_20/dsr/sck1 pio1_16/ri/ct16b0_cap0 pio0_3 pio0_19/txd/ct32b0_mat1 pio0_4/scl pio0_18/rxd/ct32b0_mat0 pio0_5/sda pio0_17/rts/ct32b0_cap0/sclk pio0_21/ct16b1_mat0/mosi1 v dd pio1_23/ct16b1_mat1/ssel1 pio1_15/dcd/ct16b0_mat2/sck1 n.c. pio0_23/ad7 n.c. v ss pio1_24/ct32b0_mat0 pio0_16/ad5/ct32b1_mat3/wakeup pio0_6/sck0 swdio/pio0_15/ad4/ct32b1_mat2 pio0_7/cts pio1_28/ct32b0_cap0/sclk pio1_22/ri/mosi1 pio1_14/dsr/ct16b0_mat1/rxd 002aah402 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 8 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller see table 3 for the full pin name. fig 4. pin configuration (lqfp64) LPC11E36FBD64/501 lpc11e37fbd64/501 lpc11e37hfbd64/401 pio1_0 v dd pio1_25 pio1_13 pio1_19 trst/pio0_14 reset/pio0_0 tdo/pio0_13 pio0_1 tms/pio0_12 pio1_7 pio1_11 v ss tdi/pio0_11 xtalin pio1_29 xtalout pio0_22 v dd pio1_8 pio0_20 swclk/pio0_10 pio1_10 pio0_9 pio0_2 pio0_8 pio1_26 pio1_21 pio1_27 pio1_2 pio1_4 v dd pio1_1 pio1_6 pio1_20 pio1_16 pio0_3 pio0_19 pio0_4 pio0_18 pio0_5 pio0_17 pio0_21 pio1_12 pio1_17 v dd pio1_23 pio1_15 n.c. pio0_23 n.c. pio1_9 pio1_24 v ss pio1_18 pio0_16 pio0_6 swdio/pio0_15 pio0_7 pio1_22 pio1_28 pio1_3 pio1_5 pio1_14 002aah403 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 9 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 6.2 pin description ta b l e 3 shows all pins and their assigned digital or analog functions in order of the gpio port number. the default function after reset is listed first. all port pins have internal pull-up resistors enabled after reset except for the true open-drain pins pio0_4 and pio0_5. every port pin has a corresponding iocon register for programming the digital or analog function, the pull-up/pull-down configurati on, the repeater, and the open-drain modes. the usart, counter/timer, and ssp functions are available on more than one port pin. table 3. pin description symbol pin hvqfn33 pin lqfp48 pin lqfp64 reset state [1] type description reset /pio0_0 2 3 4 [2] i; pu i reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. this pin also serves as the debug select input. low level selects the jtag boundary scan. high level selects the arm swd debug mode. -i/o pio0_0 ? general purpose digital input/output pin. pio0_1/clkout/ ct32b0_mat2 34 5 [3] i; pu i/o pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. -o clkout ? clockout pin. -o ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0/ioh_0 81013 [3] i; pu i/o pio0_2 ? general purpose digital input/output pin. -i/o ssel0 ? slave select for ssp0. -i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. -i/o ioh_0 ? i/o handler input/output 0. lpc11e37hfbd64/401 only. pio0_3/r/ioh_1 9 14 19 [3] i; pu i/o pio0_3 ? general purpose digital input/output pin. -- r ? reserved. -i/o ioh_1 ? i/o handler input/output 1. lpc11e37hfbd64/401 only. pio0_4/scl/ioh_2 10 15 20 [4] i; ia i/o pio0_4 ? general purpose digital input/output pin (open-drain). -i/o scl ? i 2 c-bus clock input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. -i/o ioh_2 ? i/o handler input/output 2. lpc11e37hfbd64/401 only.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 10 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller pio0_5/sda/ioh_3 11 16 21 [4] i; ia i/o pio0_5 ? general purpose digital input/output pin (open-drain). -i/o sda ? i 2 c-bus data input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. -i/o ioh_3 ? i/o handler input/output 3. lpc11e37hfbd64/401 only. pio0_6/r/ sck0/ioh_4 15 22 29 [3] i; pu i/o pio0_6 ? general purpose digital input/output pin. -- r ? reserved. -i/o sck0 ? serial clock for ssp0. -i/o ioh_4 ? i/o handler input/output 4. lpc11e37hfbd64/401 only. pio0_7/cts /ioh_5 16 23 30 [5] i; pu i/o pio0_7 ? general purpose digital input/output pin (high-current output driver). -i cts ? clear to send input for usart. -i/o ioh_5 ? i/o handler input/output 5. lpc11e37hfbd64/401 only. pio0_8/miso0/ ct16b0_mat0/r/ioh_6 17 27 36 [3] i; pu i/o pio0_8 ? general purpose digital input/output pin. -i/o miso0 ? master in slave out for ssp0. -o ct16b0_mat0 ? match output 0 for 16-bit timer 0. - - reserved. -i/o ioh_6 ? i/o handler input/output 6. lpc11e37hfbd64/401 only. pio0_9/mosi0/ ct16b0_mat1/r/ioh_7 18 28 37 [3] i; pu i/o pio0_9 ? general purpose digital input/output pin. -i/o mosi0 ? master out slave in for ssp0. -o ct16b0_mat1 ? match output 1 for 16-bit timer 0. - - reserved. -i/o ioh_7 ? i/o handler input/output 7. lpc11e37hfbd64/401 only. swclk/pio0_10/sck0/ ct16b0_mat2 19 29 38 [3] i; pu i swclk ? serial wire clock and test clock tck for jtag interface. -i/o pio0_10 ? general purpose digital input/output pin. -o sck0 ? serial clock for ssp0. -o ct16b0_mat2 ? match output 2 for 16-bit timer 0. tdi/pio0_11/ad0/ ct32b0_mat3 21 32 42 [6] i; pu i tdi ? test data in for jtag interface. -i/o pio0_11 ? general purpose digital input/output pin. -i ad0 ? a/d converter, input 0. -o ct32b0_mat3 ? match output 3 for 32-bit timer 0. table 3. pin description symbol pin hvqfn33 pin lqfp48 pin lqfp64 reset state [1] type description
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 11 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller tms/pio0_12/ad1/ ct32b1_cap0 22 33 44 [6] i; pu i tms ? test mode select for jtag interface. -i/o pio_12 ? general purpose digital input/output pin. -i ad1 ? a/d converter, input 1. -i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. tdo/pio0_13/ad2/ ct32b1_mat0 23 34 45 [6] i; pu o tdo ? test data out for jtag interface. -i/o pio0_13 ? general purpose digital input/output pin. -i ad2 ? a/d converter, input 2. -o ct32b1_mat0 ? match output 0 for 32-bit timer 1. trst /pio0_14/ad3/ ct32b1_mat1 24 35 46 [6] i; pu i trst ? test reset for jtag interface. -i/o pio0_14 ? general purpose digital input/output pin. -i ad3 ? a/d converter, input 3. -o ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio0_15/ad4/ ct32b1_mat2 25 39 52 [6] i; pu i/o swdio ? serial wire debug input/output. -i/o pio0_15 ? general purpose digital input/output pin. -i ad4 ? a/d converter, input 4. -o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio0_16/ad5/ ct32b1_mat3/ioh_8/ wakeup 26 40 53 [6] i; pu i/o pio0_16 ? general purpose digital input/output pin. -i ad5 ? a/d converter, input 5. -o ct32b1_mat3 ? match output 3 for 32-bit timer 1. -i/o ioh_8 ? i/o handler input/output 8. lpc11e37hfbd64/401 only. -i wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. pull this pin high externally before entering deep power-down mode, then pull low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio0_17/rts / ct32b0_cap0/sclk 30 45 60 [3] i; pu i/o pio0_17 ? general purpose digital input/output pin. -o rts ? request to send output for usart. -i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. -i/o sclk ? serial clock input/output for usart in synchronous mode. pio0_18/rxd/ ct32b0_mat0 31 46 61 [3] i; pu i/o pio0_18 ? general purpose digital input/output pin. -i rxd ? receiver input for usart. used in uart isp mode. -o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio0_19/txd/ ct32b0_mat1 32 47 62 [3] i; pu i/o pio0_19 ? general purpose digital input/output pin. -o txd ? transmitter output for usart. used in uart isp mode. -o ct32b0_mat1 ? match output 1 for 32-bit timer 0. table 3. pin description symbol pin hvqfn33 pin lqfp48 pin lqfp64 reset state [1] type description
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 12 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller pio0_20/ct16b1_cap0 7 9 11 [3] i; pu i/o pio0_20 ? general purpose digital input/output pin. -i ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio0_21/ct16b1_mat0/ mosi1 12 17 22 [3] i; pu i/o pio0_21 ? general purpose digital input/output pin. -o ct16b1_mat0 ? match output 0 for 16-bit timer 1. -i/o mosi1 ? master out slave in for ssp1. pio0_22/ad6/ ct16b1_mat1/miso1 20 30 40 [6] i; pu i/o pio0_22 ? general purpose digital input/output pin. -i ad6 ? a/d converter, input 6. -o ct16b1_mat1 ? match output 1 for 16-bit timer 1. -i/o miso1 ? master in slave out for ssp1. pio0_23/ad7/ioh_9 27 42 56 [6] i; pu i/o pio0_23 ? general purpose digital input/output pin. -i ad7 ? a/d converter, input 7. -i/o ioh_9 ? i/o handler input/output 9. lpc11e37hfbd64/401 only. pio1_0/ct32b1_mat0/ ioh_10 -- 1 [3] i; pu i/o pio1_0 ? general purpose digital input/output pin. -o ct32b1_mat0 ? match output 0 for 32-bit timer 1. -i/o ioh_10 ? i/o handler input/output 10. lpc11e37hfbd64/401 only. pio1_1/ct32b1_mat1/ ioh_11 -- 17 [3] i; pu i/o pio1_1 ? general purpose digital input/output pin. -o ct32b1_mat1 ? match output 1 for 32-bit timer 1. -i/o ioh_11 ? i/o handler input/output 11. lpc11e37hfbd64/401 only. pio1_2/ct32b1_mat2/ ioh_12 -- 34 [3] i; pu i/o pio1_2 ? general purpose digital input/output pin. -o ct32b1_mat2 ? match output 2 for 32-bit timer 1. -i/o ioh_12 ? i/o handler input/output 12. lpc11e37hfbd64/401 only. pio1_3/ct32b1_mat3/ ioh_13 -- 50 [3] i; pu i/o pio1_3 ? general purpose digital input/output pin. -o ct32b1_mat3 ? match output 3 for 32-bit timer 1. -i/o ioh_13 ? i/o handler input/output 13. (lpc11e37hfbd64/401 only.) pio1_4/ct32b1_cap0/ ioh_14 -- 16 [3] i; pu i/o pio1_4 ? general purpose digital input/output pin. -i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. -i/o ioh_14 ? i/o handler input/output 14. (lpc11e37hfbd64/401 only.) pio1_5/ct32b1_cap1/ ioh_15 -- 32 [3] i; pu i/o pio1_5 ? general purpose digital input/output pin. -i ct32b1_cap1 ? capture input 1 for 32-bit timer 1. -i/o ioh_15 ? i/o handler input/output 15. (lpc11e37hfbd64/401 only.) pio1_6/ioh_16 - - 64 [3] i; pu i/o pio1_6 ? general purpose digital input/output pin. -i/o ioh_16 ? i/o handler input/output 16. (lpc11e37hfbd64/401 only.) table 3. pin description symbol pin hvqfn33 pin lqfp48 pin lqfp64 reset state [1] type description
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 13 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller pio1_7/ioh_17 - - 6 [3] i; pu i/o pio1_7 ? general purpose digital input/output pin. -i/o ioh_17 ? i/o handler input/output 17. (lpc11e37hfbd64/401 only.) pio1_8/ioh_18 - - 39 [3] i; pu i/o pio1_8 ? general purpose digital input/output pin. -i/o ioh_18 ? i/o handler input/output 18. (lpc11e37hfbd64/401 only.) pio1_9 - - 55 [3] i; pu i/o pio1_9 ? general purpose digital input/output pin. pio1_10 - - 12 [3] i; pu i/o pio1_10 ? general purpose digital input/output pin. pio1_11 - - 43 [3] i; pu i/o pio1_11 ? general purpose digital input/output pin. pio1_12 - - 59 [3] i; pu i/o pio1_12 ? general purpose digital input/output pin. pio1_13/dtr / ct16b0_mat0/txd -3647 [3] i; pu i/o pio1_13 ? general purpose digital input/output pin. -o dtr ? data terminal ready output for usart. -o ct16b0_mat0 ? match output 0 for 16-bit timer 0. -o txd ? transmitter output for usart. pio1_14/dsr / ct16b0_mat1/rxd -3749 [3] i; pu i/o pio1_14 ? general purpose digital input/output pin. -i dsr ? data set ready input for usart. -o ct16b0_mat1 ? match output 1 for 16-bit timer 0. -i rxd ? receiver input for usart. pio1_15/dcd / ct16b0_mat2/sck1 28 43 57 [3] i; pu i/o pio1_15 ? general purpose digital input/output pin. i dcd ? data carrier detect input for usart. -o ct16b0_mat2 ? match output 2 for 16-bit timer 0. -i/o sck1 ? serial clock for ssp1. pio1_16/ri / ct16b0_cap0 -4863 [3] i; pu i/o pio1_16 ? general purpose digital input/output pin. -i ri ? ring indicator input for usart. -i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio1_17/ct16b0_cap1/ rxd -- 23 [3] i; pu i/o pio1_17 ? general purpose digital input/output pin. -i ct16b0_cap1 ? capture input 1 for 16-bit timer 0. -i rxd ? receiver input for usart. pio1_18/ct16b1_cap1/ txd -- 28 [3] i; pu i/o pio1_18 ? general purpose digital input/output pin. -i ct16b1_cap1 ? capture input 1 for 16-bit timer 1. -o txd ? transmitter output for usart. pio1_19/dtr /ssel1 1 2 3 [3] i; pu i/o pio1_19 ? general purpose digital input/output pin. -o dtr ? data terminal ready output for usart. -i/o ssel1 ? slave select for ssp1. pio1_20/dsr /sck1 - 13 18 [3] i; pu i/o pio1_20 ? general purpose digital input/output pin. -i dsr ? data set ready input for usart. -i/o sck1 ? serial clock for ssp1. table 3. pin description symbol pin hvqfn33 pin lqfp48 pin lqfp64 reset state [1] type description
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 14 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller pio1_21/dcd /miso1 - 26 35 [3] i; pu i/o pio1_21 ? general purpose digital input/output pin. -i dcd ? data carrier detect input for usart. -i/o miso1 ? master in slave out for ssp1. pio1_22/ri /mosi1 - 38 51 [3] i; pu i/o pio1_22 ? general purpose digital input/output pin. -i ri ? ring indicator input for usart. -i/o mosi1 ? master out slave in for ssp1. pio1_23/ct16b1_mat1/ ssel1 13 18 24 [3] i; pu i/o pio1_23 ? general purpose digital input/output pin. -o ct16b1_mat1 ? match output 1 for 16-bit timer 1. -i/o ssel1 ? slave select for ssp1. pio1_24/ct32b0_mat0 14 21 27 [3] i; pu i/o pio1_24 ? general purpose digital input/output pin. -o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_25/ct32b0_mat1 - 1 2 [3] i; pu i/o pio1_25 ? general purpose digital input/output pin. -o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_26/ct32b0_mat2/ rxd/ioh_19 -1114 [3] i; pu i/o pio1_26 ? general purpose digital input/output pin. -o ct32b0_mat2 ? match output 2 for 32-bit timer 0. -i rxd ? receiver input for usart. -i/o ioh_19 ? i/o handler input/output 18. (lpc11e37hfbd64/401 only.) pio1_27/ct32b0_mat3/ txd/ioh_20 -1215 [3] i; pu i/o pio1_27 ? general purpose digital input/output pin. -o ct32b0_mat3 ? match output 3 for 32-bit timer 0. -o txd ? transmitter output for usart. -i/o ioh_20 ? i/o handler input/output 20. (lpc11e37hfbd64/401 only.) pio1_28/ct32b0_cap0/ sclk -2431 [3] i; pu i/o pio1_28 ? general purpose digital input/output pin. -i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. -i/o sclk ? serial clock input/output for usart in synchronous mode. pio1_29/sck0/ ct32b0_cap1 -3141 [3] i; pu i/o pio1_29 ? general purpose digital input/output pin. -i/o sck0 ? serial clock for ssp0. -i ct32b0_cap1 ? capture input 1 for 32-bit timer 0. pio1_31 - 25 - [3] i; pu i/o pio1_31 ? general purpose digital input/output pin. n.c. - 19 25 - - not connected. n.c. - 20 26 - - not connected. xtalin 4 6 8 [7] - - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. table 3. pin description symbol pin hvqfn33 pin lqfp48 pin lqfp64 reset state [1] type description
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 15 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled; ia = inactive, no pull-up/dow n enabled; f = floating; if the pins are not used, tie floating pi ns to ground or power to mi nimize power consumption. [2] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. see figure 28 for the reset pad configuration. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 27 ). [4] i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with configurable pull-up/pull-down resistors and configurable hysteresis ( see figure 27 ); includes high-current output driver. [6] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 27 ); includes digital input glitch filter. [7] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptib ility to noise). leave xtalout floating. 7. functional description 7.1 on-chip flash programming memory the lpc11e3x contain up to 128 kb on-chi p flash program memory. the flash can be programmed using in-system programming (isp) or in-application programming (iap) via the on-chip boot loader software. the flash memory is divided into 4 kb sector s with each sector consisting of 16 pages. individual pages can be erased using the iap erase page command. 7.2 eeprom the lpc11e3x contain 4 kb of on-chip by te-erasable and byte -programmable eeprom data memory. the eeprom can be programmed using in-application programming (iap) via the on-chip boot loader software. 7.3 sram the lpc11e3x contain a total of 10 kb (lpc 11e37hfbd64/401) or 12 kb on-chip static ram memory. xtalout 5 7 9 [7] - - output from the oscillator amplifier. v dd 6; 29 8; 44 10; 33; 48; 58 - - supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. v ss 33 5; 41 7; 54 - - ground. table 3. pin description symbol pin hvqfn33 pin lqfp48 pin lqfp64 reset state [1] type description
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 16 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller on the lpc11e37hfbd64/401, the 2 kb sram1 region at location 0x2000 0000 to 0x2000 07fff is used for the i/o handler software library. do not use this memory location for data or other user code. 7.4 on-chip rom the on-chip rom contains the boot loader and the following application programming interfaces (apis): ? in-system programming (isp) and in-application programming (iap) support for flash including iap erase page command ? iap support for eeprom ? power profiles for configuring po wer consumption and pll settings ? 32-bit integer division routines 7.5 memory map the lpc11e3x incorporates several distinct memory regions, shown in the following figures. figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb (advanced high-performance bus) perip heral area is 2 mb in size and is divided to allow for up to 128 peripherals. the apb (a dvanced peripheral bus) peripheral area is 512 kb in size and is divided to allow for up to 32 peripherals. each peripheral of either type is allocated 16 kb of space. this addr essing scheme allows si mplifying the address decoding for each peripheral.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 17 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.6 nested vectored inte rrupt controller (nvic) the nested vectored interrupt controller (nvi c) is part of the cortex-m0. the tight coupling to the cpu allows for lo w interrupt latency and efficient processing of late arriving interrupts. 7.6.1 features ? controls system exceptions and peripheral interrupts. ? in the lpc11e3x, the nvic supp orts 24 vectored interrupts. fig 5. lpc11e3x memory map apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4004 c000 0x4005 8000 0x4005 c000 0x4006 0000 0x4006 4000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wwdt 32-bit counter/timer 0 32-bit counter/timer 1 adc usart/smart card pmu i 2 c-bus 20 - 21 reserved 10 - 13 reserved reserved reserved 25 - 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1000 0000 0x1fff 0000 0x1fff 4000 0x2000 0000 0x5000 0000 0x5000 4000 0xffff ffff reserved reserved reserved 2 kb sram2 reserved reserved 0x4000 0000 0x4008 0000 0x4008 4000 apb peripherals gpio 0x2000 4000 0x2000 4800 0x1000 2000 8 kb sram0 lpc11e3x 0x0001 8000 96 kb on-chip flash (lpc11e36) 0x0002 0000 128 kb on-chip flash (lpc11e37) 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors 002aah405 reserved reserved ssp0 ssp1 16-bit counter/timer 1 16-bit counter/timer 0 iocon system control 19 gpio interrupts 22 23 gpio group0 int 24 gpio group1 int flash/eeprom controller 0xe000 0000 0xe010 0000 private peripheral bus 2 kb sram1/ i/o handler code area for lpc11e37hfbd64/401 0x2000 0800
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 18 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller ? four programmable interrupt priority leve ls, with hardware pr iority level masking. ? software interr upt generation. 7.6.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but can have several interrupt flags. individual interrupt flags can also represent more than one interrupt source. 7.7 iocon block the iocon block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. connect peripherals to the appropriate pins be fore activating the peripheral and before enabling any related interrupt. . activity of any enabled peripheral function that is not mapped to a related pin is treated as undefined. 7.7.1 features ? programmable pull-up, pull-down, or repeater mode. ? all gpio pins (except pio0_4 and pio0_5) are pulled up to 3.3 v (v dd = 3.3 v) if their pull-up resistor is enabled. ? programmable pseudo open-drain mode. ? programmable 10 ns glitch filter on pi ns pio0_22, pio0_23, and pio0_11 to pio0_16. the glitch filter is turned on by default. ? programmable hysteresis. ? programmable input inverter. 7.8 general-purpose input/output gpio the gpio registers control device pin functions that are not connected to a specific peripheral function. pins can be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc11e3x use accelerated gpio functions: ? gpio registers are a dedicated ahb peripheral so that the fastest possible i/o timing can be achieved. ? entire port value can be written in one instruction. any gpio pin providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. the gpio block consists of three parts: 1. the gpio ports. 2. the gpio pin interrupt block to control eight gpio pins selected as pin interrupts. 3. two gpio group interrupt blocks to control two combined interrupts from all gpio pins.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 19 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.8.1 features ? gpio pins can be configured as input or output by software. ? all gpio pins default to inputs with interrupt disabled at reset. ? pin registers allow pins to be sensed and set individually. ? up to eight gpio pins can be selected from all gpio pins to create an edge- or level-sensitive gpio interrupt request. ? any pin or pins in each port can trigger a port interrupt. 7.9 i/o handler (lpc11e37hfbd64/401 only) the i/o handler is a software library-supported hardware engine for emulating serial interfaces and dma. the i/o handler can em ulate serial interfaces such as uart, i 2 c, or i 2 s with no or very low additional cpu load. the software librari es are available with supporting application notes from nxp (see http://www.lpcware.com .) lpcxpresso, keil, and iar ides are supported. i/o handler library code must be executed from the memory area 0x2000 0000 to 0x2000 07ff. this me mory is not available for other use. for application examples, see section 11.7 ? i/o handler software library applications ? . 7.10 usart the lpc11e3x contains one usart. the usart includes full modem control, su pport for synchronous mode, and a smart card interface. the rs-485/9-bit mode a llows both software address detection and automatic address detection using 9-bit mode. the usart uses a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.10.1 features ? maximum usart data bit rate of 3.125 mbit/s. ? 16 byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? support for modem control. ? support for synchronous mode. ? includes smart card interface.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 20 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.11 ssp serial i/o controller the ssp controllers operate on a ssp, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bu s during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master. in practice , often only one of these data flows carries meaningful data. 7.11.1 features ? maximum ssp speed of 25 mbit/s (master) or 4.17 mbit/s (slave) (in ssp mode) ? compatible with motorola spi (serial peripheral interface), 4-wire texas instruments ssi (serial synchronous interface), and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame 7.12 i 2 c-bus serial i/o controller the lpc11e3x contain one i 2 c-bus controller. the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each de vice is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus, and more than one bus master connected to the interface can be controlled the bus. 7.12.1 features ? the i 2 c-interface is an i 2 c-bus compliant interface with open-drain pins. the i 2 c-bus interface supports fast-mode plus with bit rates up to 1 mbit/s. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 21 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.13 10-bit adc the lpc11e3x contains one adc. it is a si ngle 10-bit successive approximation adc with eight channels. 7.13.1 features ? 10-bit successive approximation adc. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 v to v dd . ? 10-bit conversion time ? 2.44 ? s (up to 400 ksamples/s). ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead. 7.14 general purpose externa l event counter/timers the lpc11e3x includes two 32-bit counter/ti mers and two 16-bit counter/timers. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. each counter/timer also incl udes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.14.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? up to two capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event can also generate an interrupt. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? the timer and prescaler can be configured to be cleared on a designated capture event. this feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 22 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.15 system tick timer the arm cortex-m0 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 7.16 windowed watc hdog timer (wwdt) the purpose of the wwdt is to prevent an unre sponsive system state. if software fails to update the watchdog within a programmable time window, the watchdog resets the microcontroller 7.16.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time before watchdog time-out. ? software enables the wwdt, but a hardware reset or a watchdog reset/interrupt is required to disable the wwdt. ? incorrect feed sequence causes reset or interrupt, if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the irc or the dedicated watchdog oscillator (wdo). the clock sour ce selection provi des a wide range of potential timing choices of watchdog oper ation under different power conditions. 7.17 clocking and power control 7.17.1 integrated oscillators the lpc11e3x include three i ndependent oscillators: the system oscillator, the internal rc oscillator (irc), and the watchdog oscillato r. each oscillator can be used for more than one purpose as required in a particular application. following reset, the lpc11e3x o perates from the internal rc oscillator until software switches to a different clock source. the ir c allows the system to operate without any external crystal and the bootloader co de to operate at a known frequency. see figure 6 for an overview of the lpc11e3x clock generation.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 23 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.17.1.1 internal rc oscillator the irc can be used as the clock source for the wdt, and/or as the clock that drives the system pll and then the cpu. the nominal irc frequency is 12 mhz. upon power-up, any chip reset, or wake-up from deep power-down mode, the lpc11e3x use the irc as the clock source. software can later switch to one of the other available clock sources. 7.17.1.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. fig 6. lpc11e3x clocking generation block diagram watchdog oscillator irc oscillator system clock divider sysahbclkctrln (ahb clock enable) cpu, system control, pmu memories, peripheral clocks ssp0 peripheral clock divider ssp0 ssp1 peripheral clock divider ssp1 usart peripheral clock divider uart wdt wdclksel (wdt clock select) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin clkoutuen (clkout update enable) 002aah406 system clock system pll irc oscillator system oscillator watchdog oscillator mainclksel (main clock select) syspllclksel (system pll clock select) main clock irc oscillator n
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 24 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.17.1.3 watchdog oscillator the watchdog oscillator can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pin. the watchdog oscillator nominal frequency is programmable between 9.4 khz and 2.3 mhz. th e frequency spread over processing and temperature is ? 40 % (see also ta b l e 1 3 ). 7.17.2 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz. to support this frequency range, an additional divider keeps the cco within its frequency range while the pll is providing the desired output frequency. the output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. the pll output frequency must be lower than 100 mhz. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset. software can enable the pll later. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.17.3 clock output the lpc11e3x feature a clock output function that routes the irc oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.17.4 wake-up process the lpc11e3x begin operation by using the 12 mhz irc oscillator as the clock source at power-up and when awakened from deep power-down mode . this mechanism allows chip operation to resume quickl y. if the application uses the main oscillator or the pll, software must enable these comp onents and wait for them to stabilize. only then can the system use the pll and main os cillator as a clock source. 7.17.5 power control the lpc11e3x support various power control features. there are four special modes of processor power reduction: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. the cpu clock rate can also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this power cont rol mechanism allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip peripherals. this register allows fine-tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals have their own clock divider which provides even better power control. 7.17.5.1 power profiles the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile. the power configuration routine configures the lpc11e3x for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 25 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. 7.17.5.2 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and can generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, by memory systems and related controllers, and by internal buses. 7.17.5.3 deep-sleep mode in deep-sleep mode, the lpc11e3x is in sleep-mode and all peripheral clocks and all clock sources are off except for the irc. the irc output is disabled unless the irc is selected as input to the watchdog timer. in addition all analog blocks are shut down and the flash is in stand-by mode. in deep-sleep mode, the application can keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. the lpc11e3x can wake up from deep-sleep mode via reset, selected gpio pins or a watchdog timer interrupt. deep-sleep mode saves power and allows for short wake-up times. 7.17.5.4 power-down mode in power-down mode, the lpc11e3x is in sleep-mode and all peripheral clocks and all clock sources are off except for watchdog os cillator if selected. in addition all analog blocks and the flash are shut down. in powe r-down mode, the application can keep the bod circuit running for bod protection. the lpc11e3x can wake up from power-down mode via reset, selected gpio pins or a watchdog timer interrupt. power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 7.17.5.5 deep power-down mode in deep power-down mode, power is shut off to the entire chip except for the wakeup pin. the lpc11e3x can wake up from deep power-down mode via the wakeup pin. the lpc11e3x can be prevented from entering deep power-down mode by setting a lock bit in the pmu block. locking out deep powe r-down mode enables the application to keep the watchdog timer or the bod running at all times. when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. pull the reset pin high to prevent it from floating while in deep power-down mode.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 26 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.17.6 system control 7.17.6.1 reset reset has four sources on the lpc11e3x: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the irc an d initializes the flash controller. a low-going pulse as short as 50 ns resets the part. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. in deep power-down mode, an external pull-up resistor is required on the reset pin. 7.17.6.2 brownout detection the lpc11e3x includes four levels for monitoring the voltage on the v dd pin. if this voltage falls below one of the four selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for inte rrupt in the interrupt enable register in the nvic to cause a cpu interrupt. alternatively, software can monitor the signal by reading a dedicated status register. four additional threshold levels can be selected to cause a forced reset of the chip. 7.17.6.3 code security (code read protection - crp) crp provides different levels of security in th e system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. programming a specific pattern in to a dedicated flash location invokes crp. iap commands are not affected by the crp. in addition, isp entry via the pio0_1 pin can be disabled without enabling crp. for details, see the lpc11exx user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 selected , fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin as well. if necessary, the application must provide a flash update mechanism using iap calls or using a call to the reinvoke isp command to enable flash update via the usart.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 27 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller in addition to the three crp levels, sampli ng of pin pio0_1 for valid user code can be disabled. for details, see the lpc11exx user manual . 7.17.6.4 apb interface the apb peripherals are located on one apb bus. 7.17.6.5 ahblite the ahblite connects the cpu bus of the arm cortex-m0 to the flash memory, the main static ram, and the rom. 7.17.6.6 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 28 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 7.18 emulation and debugging debug functions are integrated into the arm co rtex-m0. serial wire debug functions are supported in addition to a standard jt ag boundary scan. the arm cortex-m0 is configured to support up to four breakpoints and two watch points. the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd debug port is disabled while the lpc11e3x is in reset. to perform boundary scan testing, follow these steps: 1. erase any user code residing in flash. 2. power up the part with the reset pin pulled high externally. 3. wait for at least 250 ? s. 4. pull the reset pin low externally. 5. perform boundary scan operations. 6. once the boundary scan operations are completed, assert the trst pin to enable the swd debug mode, and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 29 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. c) the limiting values are stress ratings onl y. operating the part at these values is not recommended, and proper operation is n ot guaranteed. the conditions for functi onal operation are specified in table 5 . [2] maximum/minimum voltage above the maximum operating voltage (see table 5 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] see table 6 for maximum operating voltage. [4] v dd present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd is powered down. [5] including voltage on outputs in 3-state mode. [6] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. please refer to t he jedec spec (j-std-033b.1) for further details. [7] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 4. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) [2] ? 0.5 +4.6 v v i input voltage 5 v tolerant digital i/o pins; v dd ? 1.8 v [5] [2] ? 0.5 +5.5 v v dd = 0 v ? 0.5 +3.6 v 5 v tolerant open-drain pins pio0_4 and pio0_5 [2] [4] ? 0.5 +5.5 v ia analog input voltage pin configured as analog input [2] [3] ? 0.5 4.6 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ?c -1 0 0m a t stg storage temperature non-operating [6] ? 65 +150 ? c t j(max) maximum junction temperature -150 ? c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [7] -+ 6 5 0 0v
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 30 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 9. static characteristics table 5. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) 1.8 3.3 3.6 v i dd supply current active mode; v dd =3.3v; t amb =25 ? c; code while(1){} executed from flash; system clock = 12 mhz [2] [3] [4] [5] [6] -2-ma system clock = 50 mhz [3] [4] [5] [6] -7-ma sleep mode; v dd = 3.3 v; t amb =25 ?c; system clock = 12 mhz [2] [3] [4] [5] [6] -1-ma deep-sleep mode; v dd = 3.3 v; t amb =25 ?c [3] - 300 - ? a power-down mode; v dd =3.3v; t amb =25 ?c -2- ? a deep power-down mode; v dd =3.3v; t amb =25 ?c [8] - 220 - na standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.510na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.510na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510na v i input voltage pin configured to provide a digital function; v dd ? 1.8 v [9] [10] 0- 5.0v v dd = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage 2.0 v ? v dd ? 3.6 v; i oh = ? 4 ma v dd ? 0.4 - - v 1.8 v ? v dd < 2.0 v; i oh = ? 3 ma v dd ? 0.4 - - v v ol low-level output voltage 2.0 v ? v dd ? 3.6 v; i ol =4 ma - - 0.4 v 1.8 v ? v dd < 2.0 v; i ol =3 ma - - 0.4 v i oh high-level output current v oh =v dd ? 0.4 v; 2.0 v ? v dd ? 3.6 v ? 4- - ma 1.8 v ? v dd < 2.0 v ? 3- - ma
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 31 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller i ol low-level output current v ol =0.4v 2.0 v ? v dd ? 3.6 v 4- - ma 1.8 v ? v dd < 2.0 v 3 - - ma i ohs high-level short-circuit output current v oh =0v [11] -- ? 45 ma i ols low-level short-circuit output current v ol =v dd [11] --50ma i pd pull-down current v i = 5 v 10 50 150 ? a i pu pull-up current v i =0v; 2.0 v ? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a 1.8 v ? v dd < 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 32 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] irc enabled; system oscillator disabled; system pll disabled. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] bod disabled. [5] all peripherals disabled in the ahbclkctrl register. peri pheral clocks to usart, ssp0/1 disabled in the syscon block. [6] low-current mode pwr_low_current selected when runni ng the set_power routine in the power profiles. [7] irc disabled; system oscill ator enabled; system pll enabled. [8] wakeup pin pulled high externally. an exter nal pull-up resistor is required on the reset pin for the deep power-down mode. [9] including voltage on outputs in 3-state mode. [10] 3-state outputs go into 3-state mode in deep power-down mode. [11] allowed as long as the current limit does not exceed the maximum current allowed by the device. [12] to v ss . i pu pull-up current v i =0v 2.0 v ? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a 1.8 v ? v dd < 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 33 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 7 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 7 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 7 . [5] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 7 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 7 . [7] t amb = 25 ? c; maximum sampling frequency f s = 400 ksamples/s and analog input capacitance c ia = 1 pf. [8] input resistance r i depends on the sampling frequency fs: r i = 1 / (f s ? c ia ). table 6. adc static characteristics t amb = ? 40 ? c to +85 ? c unless otherwise specified; adc frequency 4.5 mhz, v dd = 2.5 v to 3.6 v. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] --? 1lsb e l(adj) integral non-linearity [3] --? 1.5 lsb e o offset error [4] --? 3.5 lsb e g gain error [5] --0 . 6% e t absolute error [6] --? 4lsb r vsi voltage source interface resistance --40k ? r i input resistance [7] [8] --2 . 5m ?
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 34 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 7. adc characteristics 002aaf426 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd ? v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 35 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 9.1 bod static characteristics [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see the lpc11exx user manual . 9.2 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see the lpc11exx user manual ): ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpiondata registers to drive the outputs low. table 7. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 1 assertion - 2.22 - v de-assertion - 2.35 - v interrupt level 2 assertion - 2.52 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.80 - v de-assertion - 2.90 - v reset level 0 assertion - 1.46 - v de-assertion - 1.63 - v reset level 1 assertion - 2.06 - v de-assertion - 2.15 - v reset level 2 assertion - 2.35 - v de-assertion - 2.43 - v reset level 3 assertion - 2.63 - v de-assertion - 2.71 - v
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 36 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; bod disabled; all peripher als disabled in the sysahbclkctrl register; all peripheral clocks disabled; low-current mode. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 8. typical supply current versus regulator supply voltage v dd in active mode conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; bo d disabled; all peripherals di sabled in the sysahbclkctrl register; all peripheral clocks disabled; low-current mode. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 9. typical supply current versus temperature in active mode v dd (v) 1.8 3.6 3.0 2.4 002aag749 3 6 9 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) temperature (c) -40 85 35 10 60 -15 002aag750 3 6 9 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 37 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; sleep mode entered from flash; internal pull-up resistors disabled; bod disabled; all peripherals disabled in the sysahbclkc trl register; all peripher al clocks disabled; low-current mode.. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 10. typical supply current ver sus temperature in sleep mode conditions: bod disabled; all oscillators and analog blocks turned off in the pdsleepcfg register. fig 11. typical supply current versus temperature in deep-sleep mode 002aag751 temperature (c) -40 85 35 10 60 -15 1 3 2 4 i dd (ma) 0 12 mhz (1) 36 mhz (2) 48 mhz (2) 24 mhz (2) 002aag745 temperature (c) -40 85 35 10 60 -15 355 375 365 385 i dd (a) 345 v dd = 3.6 v v dd = 3.3 v v dd = 2.0 v v dd = 1.8 v
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 38 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 9.3 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator an d pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 48 mhz. conditions: bod disabled; all oscillators and analog blocks turned off in the pdsleepcfg register. fig 12. typical supply current versus temperature in power-down mode fig 13. typical supply current versus temperature in deep power-down mode 002aag746 temperature (c) -40 85 35 10 60 -15 5 15 10 20 i dd (a) 0 v dd = 3.6 v, 3.3 v v dd = 2.0 v v dd = 1.8 v 002aag747 temperature (c) -40 85 35 10 60 -15 0.2 0.6 0.4 0.8 i dd (a) 0 v dd = 3.6 v v dd = 3.3 v v dd = 2.0 v v dd = 1.8 v
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 39 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller table 8. power consumption for individual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 48 mhz irc 0.27 - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.22 - - irc running; pll off; independent of main clock frequency. watchdog oscillator at 500 khz/2 0.004 - - system oscillator running; pll off; independent of main clock frequency. bod 0.051 - - independent of main clock frequency. main pll - 0.21 - - adc - 0.08 0.29 - clkout - 0.12 0.47 main clock divided by 4 in the clkoutdiv register. ct16b0 - 0.02 0.06 - ct16b1 - 0.02 0.06 - ct32b0 - 0.02 0.07 - ct32b1 - 0.02 0.06 - gpio - 0.23 0.88 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. ioconfig - 0.03 0.10 - i 2 c - 0.04 0.13 - rom - 0.04 0.15 - spi0 - 0.12 0.45 - spi1 - 0.12 0.45 - uart - 0.22 0.82 - wwdt - 0.02 0.06 main clock select ed as clock source for the wdt.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 40 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 9.4 electrical pi n characteristics conditions: v dd = 3.3 v; on pin pio0_7. fig 14. high-drive output: typical high-level output voltage v oh versus high-level output current i oh . conditions: v dd = 3.3 v; on pins pio0_4 and pio0_5. fig 15. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 41 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; standard port pins and pio0_7. fig 16. typical low-l evel output current i ol versus low-level output voltage v ol conditions: v dd = 3.3 v; standard port pins. fig 17. typical high-level output voltage v oh versus high-level output source current i oh v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 42 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 18. typical pull-up current i pu versus input voltage v i conditions: v dd = 3.3 v; standard port pins. fig 19. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae988 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd (a) 0 t = 85 c 25 c ?40 c
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 43 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 10. dynamic characteristics 10.1 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to the flash. data must be written to the flash in blocks of 256 bytes. 10.2 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 9. flash characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 10. eeprom characteristics t amb = ? 40 ? cto+85 ? c; v dd = 2.7 v to 3.6 v. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance 100000 1000000 - cycles t ret retention time powered 100 200 - years unpowered 150 300 - years t prog programming time 64 bytes - 2.9 - ms table 11. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ? c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 44 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 10.3 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. fig 20. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 table 12. dynamic char acteristics: irc t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd ? 3.6 v [1] . symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz ? 1 % accuracy is guaranteed for 2.7 v ? v dd ? 3.6 v and t amb = ?40 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 21. internal rc oscillator frequency versus temperature 002aaf403 11.95 12.05 12.15 f (mhz) 11.85 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v 2.0 v
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 45 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the lpc11exx user manual. 10.4 i/o pins [1] applies to standard port pins and reset pin. 10.5 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. table 13. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4-khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz table 14. dynamic characteristics: i/o pins [1] t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 15. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [3] [4] [5] [6] of both sda and scl signals standard-mode -3 0 0n s fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3] [7] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 46 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller [2] parameters are valid over operating tem perature range unless otherwise specified. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [4] c b = total capacitance of one bus line in pf. [5] the maximum t f for the sda and scl bus lines is s pecified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [6] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. [7] thd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowl edge. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if th e device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] tsu;dat is the data set-up time that is measured with respec t to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. fig 22. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 47 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 10.6 ssp interface [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the spi peripheral clock divider (sspclkdiv), the spi scr parameter (specified in the ssp0cr0 register), and the spi cpsdvsr parameter (specified in the spi clock prescale register). [2] t amb = ?40 ? c to 85 ? c. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; for normal voltage supply range: v dd = 3.3 v. table 16. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit spi master (in spi mode) t cy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 ns t ds data set-up time in spi mode 2.4 v ? v dd ? 3.6 v [2] 15 - - ns 2.0 v ? v dd < 2.4 v [2] 20 ns 1.8 v ? v dd < 2.0 v [2] 24 - - ns t dh data hold time in spi mode [2] 0-- n s t v(q) data output valid time in spi mode [2] -- 1 0 n s t h(q) data output hold time in spi mode [2] 0-- n s spi slave (in spi mode) t cy(pclk) pclk cycle time 20 - - ns t ds data set-up time in spi mode [3] [4] 0-- n s t dh data hold time in spi mode [3] [4] 3 ? t cy(pclk) + 4 - - ns t v(q) data output valid time in spi mode [3] [4] -- 3 ? t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -- 2 ? t cy(pclk) + 5 ns
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 48 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller fig 23. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 49 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller fig 24. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 50 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 11. application information 11.1 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv (rms) is needed. in slave mode, couple the input clock signal with a capacitor of 100 pf ( figure 25 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this signal corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configuration can be left unconnected. external components and models used in oscillation mode are shown in figure 26 and in ta b l e 1 7 and ta b l e 1 8 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (l, c l and r s represent the fundamental frequency). capacitance c p in figure 26 represents the parallel package capacitance and must not be larger than 7 pf . parameters f osc , c l , r s and c p are supplied by the crystal manufacturer. fig 25. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 51 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 11.2 xtal printed-circuit bo ard (pcb) layout guidelines follow these guidelin es for pcb layout: ? connect the crystal on the pcb as close as possible to the oscilla tor input and output pins of the chip. ? take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal use have a common ground plane. fig 26. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 17. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz to 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz to 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz to 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz to 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 18. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz to 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz to 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 52 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller ? connect the external components to the ground plain. ? to keep parasitics and the noise coupled in via the pcb as small as possible, keep loops as small as possible. ? choose smaller values of c x1 and c x2 if parasitics of the pcb layout increase. 11.3 standard i/o pad configuration figure 27 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input fig 27. standard i/o pad configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input 002aaf695 pin configured as digital output driver pin configured as digital input pin configured as analog input 10 ns rc glitch filter
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 53 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 11.4 reset pad configuration 11.5 adc effective input impedance a simplified diagram of the adc input channel s can be used to determine the effective input impedance seen from an external voltage source. see figure 29 . the effective input impedance, r in , seen by the external voltage source, v ext , is the parallel impedance of ((1/f s x c ia ) + r mux + r sw ) and (1/f s x c io ), and can be calculated using equation 1 with f s = sampling frequency c ia = adc analog input capacitance r mux = analog mux resistance r sw = switch resistance c io = pin capacitance (1) fig 28. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin fig 29. adc input channel c ia r s v ss v ext 002aah615 adc comparator adc block r in c io r mux r sw source <2 k <1.3 k r in 1 f s c ia ? ----------------- - r mux r sw ++ ?? ?? 1 f s c io ? ----------------- - ?? ?? ?? =
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 54 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller under nominal operating condition v dd = 3.3 v and with the maximum sampling frequency fs = 400 khz, the parame ters assume the following values: c ia = 1 pf (max) r mux = 2 k ? (max) r sw = 1.3 k ? (max) c io = 7.1 pf (max) the effective input impedance with these parameters is r in = 308 k ? . 11.6 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 6 : ? the adc input trace must be short and as close as possible to the lpc11e3x chip. ? shield the adc input traces from fast switching digital signals and noisy power supply lines. ? the adc and the digital core share the same power supply. therefore, filter the power supply line adequately. ? to improve the adc performance in a noisy environment, put the device in sleep mode during the adc conversion. 11.7 i/o handler software library applications the following sections provide application exam ples for the i/o hand ler software library. all library examples make use of the i/o handler hardware to extend the functionality of the part through software library calls. the library is available on http://www.lpcware.com . 11.7.1 i/o handler i 2 s the i/o handler software library provides functions to emulate an i 2 s master transmit interface using the i/o handler hardware block. the emulated i 2 s interface loops over a 1 kb buffer, transmitting the datawords according to the i 2 s protocol. interrupts are generated every time when the first 512 bytes have been transmitted and when the last 512 bytes have been transmitted. this allows the arm core to load the free portion of the buffer with new data, thereby enabling streaming audio. two channels with 16-bit per channel are supported. the code size of the software library is 1 kb and code must be executed from the sram1 memory area reserved for the i/o handler code. 11.7.2 i/o handler uart the i/o handler uart library emulates one additional full-duplex uart. the emulated uart can be configured for 7 or 8 data bits, no parity and 1 or 2 stop bits. the baud rate is configurable up to 115200 baud. the rxd signal is available on three i/o handler pins (ioh_6, ioh_16, ioh_20), while txd and cts are available on all 21 i/o handler pins. the code size of the software library is abou t 1.2 kb and code must be executed from the sram1 memory area reserved for the i/o handler code.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 55 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 11.7.3 i/o handler i 2 c the i/o handler i 2 c library allows to have an additional i 2 c-bus master. i 2 c read, i 2 c write and combined i 2 c read/write are supported. data is au tomatically read from and written to user-defined buffers. the i/o handler i 2 c library combined with the on-chip i 2 c module allows to have two distinct i 2 c buses, allowing to separa te low-speed from high-speed devices or bridging two i 2 c buses. 11.7.4 i/o handler dma the i/o handler dma library of fers dma-like functionality. four types of transfer are supported: memory to memory, memory to peripheral, peripheral to memory and peripheral to peripheral. supported peri pherals are usart, ssp0/1, adc and gpio. dma transfers can be triggered by the source/target peripheral, software, counter/timer module ct16b1, or i/o handler pin pio1_6/ioh_16.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 56 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 12. package outline fig 30. package outline hvqfn33 (7 x 7 x 0.85 mm) references outline version european projection issue date iec jedec jeita - - - hvqfn33_po 09-03-17 09-03-23 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm a 1 b 0.35 0.28 0.23 cd (1) d h e (1) e h 4.85 4.70 4.55 ee 1 e 2 4.55 lv 0.1 w 0.05 y 0.08 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a 1 a c b e 2 e 1 e e ac b v c w terminal 1 index area d h e h l 9 16 32 33 25 17 24 8 1
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 57 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller fig 31. package outline lqfp48 (sot313-2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 58 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller fig 32. package outline lqfp64 (sot314-2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1)(1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 59 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 13. soldering fig 33. reflow soldering for the hvqfn33 (7x7) package footprint information for reflow soldering of hvqfn33 package 001aao134 occupied area solder land solder resist solder land plus solder paste solder paste deposit dimensions in mm remark: stencil thickness: 0.125 mm e = 0.65 evia = 4.25 owdtot = 5.10 oa pid = 7.25 pa+oa oid = 8.20 oa 0.20 sr chamfer (4) 0.45 dm evia = 1.05 w = 0.30 cu evia = 4.25 evia = 2.40 lbe = 5.80 cu lbd = 5.80 cu pie = 7.25 pa+oa lae = 7.95 cu lad = 7.95 cu oie = 8.20 oa owetot = 5.10 oa ehs = 4.85 cu dhs = 4.85 cu 4.55 sr 4.55 sr b-side (a-side fully covered) number of vias: 20 solder resist covered via 0.30 ph 0.60 sr cover 0.60 cu sehtot = 2.70 sp sdhtot = 2.70 sp gape = 0.70 sp spe = 1.00 sp 0.45 dm spd = 1.00 sp gapd = 0.70 sp
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 60 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller fig 34. reflow soldering for the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 61 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller fig 35. reflow soldering for the lqfp64 package sot314-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp64 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 62 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 14. revision history table 19. revision history document id release date data sheet status change notice supersedes lpc11e3x v.2.2 20140114 product data sheet - lpc11e3x v.1.2 modifications: isp mode removed from pin pio0_3 in ta b l e 3 . lpc11e3x v.2.1 20131230 product data sheet - lpc11e3x v.1.1 modifications: add reserved function to pins pio0_8/miso0/ct 16b0_mat0/r/ioh_6 and pio0_9/mosi0/ct16b0_mat1/r/ioh_7. lpc11e3x v.2 20131121 product data sheet - lpc11e3x v.1.1 modifications: ? parts lpc11e3hfbd64/401 added. ? 8 kb sram block at 0x1000 000 renamed to sram0 in figure 5. ? i/o handler pins added in table 3. ? typical range of watchdog oscillator frequency changed to 9.4 khz to 2.3 mhz. ? section 11.7 ?i/o handler soft ware library applications? added. ? condition v dd = 0 v added to parameter v i in table 5 for clarity. lpc11e3x v.1.1 20130924 product data sheet - lpc11e3x v.1 modifications: ? table 3: added ?5 v to lerant pad? to reset /pio0_0 table note. ? table 7: removed bod interrupt level 0. ? added section 11.5 ?adc effective input impedance?. ? programmable glitch filter is enab led by default. see section 7.7.1. ? table 5 ?static characteristics? added pin capacitance section. ? table 4 ?limiting values?: ? updated v dd min and max. ? updated v i conditions. ? table 10 ?eeprom characteristics?: ? removed f clk and t er ; the user does not have control over these parameters. ? changed the t prog from 1.1 ms to 2.9 ms; the eepr om iap always does an erase and program, thus the total program time is t er + t prog . lpc11e3x v.1 20121107 objective data sheet - -
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 63 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 64 of 66 nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc11e3x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2.2 ? 14 january 2014 65 of 66 continued >> nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 functional description . . . . . . . . . . . . . . . . . . 15 7.1 on-chip flash programming memory . . . . . . . 15 7.2 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 nested vectored interrupt controller (nvic) . 17 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18 7.7 iocon block . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.8 general-purpose input/output gpio . . . . . . . 18 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.9 i/o handler (lpc11e37hfbd64/401 only) . . 19 7.10 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 ssp serial i/o controller . . . . . . . . . . . . . . . . . 20 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 20 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.13 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 general purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . 21 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15 system tick timer . . . . . . . . . . . . . . . . . . . . . . 22 7.16 windowed watchdog timer (wwdt) . . . . . . 22 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 clocking and power control . . . . . . . . . . . . . . 22 7.17.1 integrated oscillators . . . . . . . . . . . . . . . . . . . 22 7.17.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 23 7.17.1.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 23 7.17.1.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 24 7.17.2 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.17.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.17.4 wake-up process . . . . . . . . . . . . . . . . . . . . . . 24 7.17.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.17.5.1 power profiles . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.17.5.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.17.5.3 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 25 7.17.5.4 power-down mode . . . . . . . . . . . . . . . . . . . . . 25 7.17.5.5 deep power-down mode . . . . . . . . . . . . . . . . 25 7.17.6 system control . . . . . . . . . . . . . . . . . . . . . . . . 26 7.17.6.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.17.6.2 brownout detection . . . . . . . . . . . . . . . . . . . . 26 7.17.6.3 code security (code read protection - crp) . . . . . . . . . . . 26 7.17.6.4 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17.6.5 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17.6.6 external interr upt inputs . . . . . . . . . . . . . . . . . 27 7.18 emulation and debugging . . . . . . . . . . . . . . . 28 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29 9 static characteristics . . . . . . . . . . . . . . . . . . . 30 9.1 bod static characteristics . . . . . . . . . . . . . . . 35 9.2 power consumption . . . . . . . . . . . . . . . . . . . 35 9.3 peripheral power consumption . . . . . . . . . . . 38 9.4 electrical pin characteristics. . . . . . . . . . . . . . 40 10 dynamic characteristics. . . . . . . . . . . . . . . . . 43 10.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 43 10.3 internal oscillators . . . . . . . . . . . . . . . . . . . . . 44 10.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.6 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 application information . . . . . . . . . . . . . . . . . 50 11.1 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2 xtal printed-circuit board (pcb) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3 standard i/o pad configuration . . . . . . . . . . . 52 11.4 reset pad configuration . . . . . . . . . . . . . . . . . 53 11.5 adc effective input impedance . . . . . . . . . . . 53 11.6 adc usage notes. . . . . . . . . . . . . . . . . . . . . . 54 11.7 i/o handler software library applications . . . . 54 11.7.1 i/o handler i 2 s. . . . . . . . . . . . . . . . . . . . . . . . 54 11.7.2 i/o handler uart . . . . . . . . . . . . . . . . . . . . . 54 11.7.3 i/o handler i 2 c. . . . . . . . . . . . . . . . . . . . . . . . 55 11.7.4 i/o handler dma . . . . . . . . . . . . . . . . . . . . . . 55 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 56 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 62 15 legal information . . . . . . . . . . . . . . . . . . . . . . 63 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 63 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 63
nxp semiconductors lpc11e3x 32-bit arm cortex-m0 microcontroller ? nxp b.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 14 january 2014 document identifier: lpc11e3x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16 contact information. . . . . . . . . . . . . . . . . . . . . 64 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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